Email this article An efficient and analytical approach for soft error rate estimation in digital circuits
Abstract
Soft errors due to cosmic rays cause reliability problems during lifetime operation of digital systems, which increase exponentially with Moore’s law. The first step in developing efficient soft error tolerant schemes is to analyze the effect of soft errors at the system level. This enhanced concept develops a systematic approach for soft error rate estimation. The proposed framework is divided in two stages. First, signal probabilities are computed via a hybrid approach combining heuristics and selective simulation of reconvergent subnets. In the second stage, signal probabilities are used to compute the vulnerability of all the gates in a combinational block using a incremental algorithm Experiments on benchmark circuits and comparison of the results with random fault injection (previous work) show that proposed method is accurate while orders of magnitude faster.
References
S. Almukhaizim, Y. Makris, Y. S. Yang, and A. Veneris, “Seamless Integration of SER in Rewiring-Based Design Space Exploration,†in Proc. International Test Conference, 2006, pp. 1–9.
G. Asadi and M. B. Tahoori, “An Accurate SER Estimation Method Based on Propagation Proba- bility,†Proc. Design Automation and Test in Europe Conf, pp. 306–307, 2005
V. Carreno, G. Choi, and R. K. Iyer, “Analog-Digital Simulation of Transient-Induced Logic Er- rors and Upset Susceptibility of an Advanced Con- trol System,†in NASA Technical Memo 4241, 1990.
D. L. Chenette, J. Chen, E. Clayton, T. G. Guzik, J. P. Wefel, M. Garcia-Munoz, C. Lopate, K. R. Pyle, K. P. Ray, E. G. Mullen, and D. A. Hardy, “The CRRES/SPACERAD Heavy Ion Model of the Environment (CHIME) for Cosmic Ray and Solar Particle Effects on Electronic and Biological Systems in Space,†IEEE Trans. on Nuclear Science , vol. 41, no. 6, pp. 2332–2339, 1994.
A. Dharchoudhury, S. M. Kang, H. Cha, and J. H. Patel, “Fast Timing Simulation of Transient Faults in Digital Circuits,†in Proc. IEEE/ACM International Conference on Computer-Aided Design, 1994, pp. 719–722.
P. E. Dodd, F. W. Sexton, G. L. Hash, M. R. Shaneyfelt, B. L. Draper, A. J. Farino, and R. S. Flores, “Impact of Technology Trends on SEU in CMOS SRAMs,†IEEE Trans. Nuclear Science, vol. 43, no. 6, pp. 2797–2804, Dec. 1996.
Graham, “Soft errors a prob- lem as SRAM geometries shrink,†http://www.ebnews.com/story/OEG20020128S0079, ebn, 28 Jan 2002.
K. J. Hass and J. W. Ambles, “Single Event Tran- sients in Deep Submicron CMOS,†1999.
T. Heijmen and A. Nieuwland, “Soft-Error-Rate Testing of Deep-Submicron Integrated Circuits,†in Proc. Eleventh IEEE European Test Symposium, 2006, pp. 247–252.
B. Ingols and A. Rambaud, “iRoC Releases Ro- bust SPARC Test Report,†http://www.us.designreuse. com/news/news65.html, 2002.
Refbacks
- There are currently no refbacks.
Copyright © 2013, All rights reserved.| ijseat.com
International Journal of Science Engineering and Advance Technology is licensed under a Creative Commons Attribution 3.0 Unported License.Based on a work at IJSEat , Permissions beyond the scope of this license may be available at http://creativecommons.org/licenses/by/3.0/deed.en_GB.
Â