Switching Activity Reduction Technique In Soc Testing

P. Sai Kumar, N S Govind

Abstract


This paper discusses the generation Pseudo Random number generation using Low Power Linear Feedback Shift Resister (LFSR) which is more suitable for Built-In-Test (BIT) structures used for testing of VLSI circuits.  BIT is a design for testability (DFT) technique in which testing is carried out using built in hardware features. Since testing is built into the hardware, it is faster and efficient.  The proposed test pattern generator reduces the switching activity among the test patterns.


References


B. Chappell, “The Fine Art of IC Design,†IEEE Spectrum, vol. 36, no. 7, July 1999, pp. 30-34.

A. Crouch, Design-for-Test for Digital IC’s and Embedded Core Systems, Prentice Hall, Upper Saddle River, N.J., 1999.

Y. Zorian, “A Distributed BIST Control Scheme for Complex VLSI Devices,†Proc. 11th IEEE VLSI Test Symp. (VTS 93), IEEE CS Press, Los Alamitos, Calif., 1993, pp. 4-9.

‘

J. Rajski and J. Tyszer, Arithmetic Built-In Self- Test for Embedded Systems, Prentice Hall PTR, Upper Saddle River, N.J., 1998.

M.L. Bushnell and V.D. Agrawal, Essentials of Electronic Testing, Kluwer Academic, Boston, 2000, p. 14.

S. Wang and S.K. Gupta, “DS-LFSR: A New BIST TPG for Low Heat Dissipation,†Proc. Int’l Test Conf. (ITC 97), IEEE Press, Piscataway, N.J., 1997, pp. 848-857.

J. Monzel et al., “Power Dissipation During Testing: Should We Worry About It?†Proc. 15th IEEE VLSI Test Symp. (VTS 97), IEEE CS Press, Los Alamitos, Calif., 1997, p. 456.

T.W. Williams et al., “IDDQ Test: Sensitivity Analysis

of Scaling,†Proc. Int’l Test Conf. (ITC 96), IEEE Press, Piscataway, N.J., 1996, pp. 786-792.

M.A. Cirit, “Estimating Dynamic Power Consumption

of CMOS Circuits,†Proc. Int’l Conf. Computer-Aided Design (ICCAD 87), IEEE CS Press, Los Alamitos, Calif., 1987, pp. 534-537.

C.Y. Wang and K. Roy, “Maximum Power Estimationfor CMOS Circuits Using Deterministic and Statistical Approaches,†Proc. 9th IEEE VLSIConf., IEEE CS Press, Los Alamitos, Calif., 1995,pp. 364-369.

N.H.E. Weste, K. Eshraghian, and M.J.S. Smith, Principles of CMOS VLSI Design: A Systems Perspective,Addison-Wesley Longman, Reading,Mass., 2000.

A. Krstic, K.T. Cheng, and S.T. Chakradhar, “Testing

High Speed VLSI Devices Using Slower Testers,†Proc. 17th VLSI Test Symp. (VTS 99), IEEE CS Press, Los Alamitos, Calif., 1999, pp. 16-21.

R. Parkar, “Bare Die Test,†Proc. IEEE Multi-Chip

Module Conf., IEEE CS Press, Los Alamitos, Calif., 1992, pp. 24-27.

H. Cheung and S. Gupta, “A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation,†Proc. Int’l Test Conf. (ITC 96),IEEE Press, Piscataway, N.J., 1996, pp. 22-32.

H.J. Wunderlich, “BIST for Systems-on-a-Chip,†Integration: The VLSI J., vol. 26, nos. 1-2, Dec.n 1998, pp. 55-78.

A. Hertwig and H.J. Wunderlich, “Low Power Serial

Built-In Self-Test,†Proc. 3rd European Test Workshop (ETW 98), IEEE CS Press, Los Alamitos, Calif., 1998, pp. 49-53.

S. Wang and S.K. Gupta, “ATPG for Heat Dissipation

Minimization During Test Application,†IEEE Trans. Computers, vol. 47, no. 2, Feb. 1998, pp.256-262.

S. Wang and S.K. Gupta, “ATPG for Heat Dissipation

Minimization for Scan Testing,†Proc. 34th ACM/IEEE Design Auto. Conf. (DAC 97), ACM Press, New York, 1997, pp. 614-619.

F. Corno et al., “A Test Pattern Generation Methodology for Low Power Consumption,†Proc. 16th VLSI Test Symp. (VTS 98), IEEE CS Press, Los Alamitos, Calif., 1998, pp 453-459.

S. Chakravarty and V. Dabholkar, “Minimizing Power Dissipation in Scan Circuits During Test Application,†Proc. IEEE Int’l Workshop on Low Power Design, IEEE CS Press, Los Alamitos, Calif., 1994, pp. 51-56.

P. Girard et al., “Reducing Power Consumption during Test Application by Test Vector Ordering,†Proc. Int’l Symp. Circuits and Systems (ISCAS 98), Part II, IEEE CS Press, Los Alamitos, Calif., 1998, pp. 296-299.

P. Girard et al., “A Test Vector Ordering Technique

for Switching Activity Reduction during TestOperation,†Proc. 9th Great Lakes Symp. on VLSI(GLS-VLSI 99), IEEE CS Press, Los Alamitos,Calif., 1999, pp. 24-27.

V. Dabholkar et al., “Techniques for Reducing Power Dissipation During Test Application in Full Scan Circuits,†IEEE Trans. Computer-Aided Design, vol. 17, no. 12, Dec. 1998, pp. 1325-1333.

Y. Bonhomme et al., “Scan Cell Ordering for Low Power Scan Testing,†to be published in Proc. 7th European Test Workshop (ETW 02), IEEE CS Press, Los Alamitos, Calif., 2002.

T.C. Huang and K.J. Lee, “An Input Control Techniquefor Power Reduction in Scan Circuits During Test Application,†Proc. 8th Asian Test


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