Power Optimized CNN Based CAM Using Clock Gating Techniques

K. SaiLakshmi, K.Siva Nagendra

Abstract


A Content Addressable Memory(CAM) is a Memory used in certain very high speed searchapplications. It compares input data against a table of stored data, and returns the address of matching data.Since basic look up table functions performed overall the stored memory information there is a high power dissipation. The proposed clock gating technique to reduce the power consumption. Since delay buffers are accessed sequentially, it adopts ring counter addressing scheme. In the ring counter D- Flip flops are usedare utilized to reduce power consumption

References


A. Agarwal, S. Hsu, S. Mathew, M. Anders, H. Kaul, F. Sheikh, and R. Krishnamurthy, “A 128x128b high-speed wide-and match-line content addressable memory in 32nm CMOS,†in ESSCIRC (ESSCIRC), 2011Proceedings of the, Sep. 2011, pp. 83–86.

N.-F. Huang, W.-E.Chen, J.-Y.Luo, and J.-M. Chen, “Design of multi-field IPv6 packet classifiers using ternary CAMs,†in Global Telecommunications Conference, 2001. GLOBECOM ’01. IEEE, vol. 3,2001, pp. 1877–1881.

N. Onizawa, S. Matsunaga, V. C. Gaudet, and T. Hanyu, “High throughput low-energy content-addressable memory based on self-time overlapped search mechanism,†in Proc. International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2012, pp. 41–48.

C.-S. Lin, J.-C.Chang, and B.-D. Liu, “A low-power pre computation based fully parallel content-addressable memory,†IEEE Journal of Solid-State Circuits, vol. 38, no. 4, pp. 654 – 662, Apr. 2003.

S.-J. Ruan, C.-Y.Wu, and J.-Y. Hsieh, “Low power design of pre computation-based content-addressable memory,†Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 16, no. 3, pp.331–335, Mar. 2008.

K. Pagiamtzis and A. Sheikholeslami, “Content-addressable memory(CAM) circuits and architectures: a tutorial and survey,†Solid-State Circuits, IEEE Journal of, vol. 41, no. 3, pp. 712–727, march 2006.

H. Jarollahi, N. Onizawa, V. Gripon, and W. J. Gross, “Architecture and implementation of an associative memory using sparse clustered networks,†in IEEE International Symposium on Circuits and Systems(ISCAS), Seoul, Korea, May 2012, pp. 2901–2904.

J.-S. Wang, H.-Y.Li, C.-C.Chen, and C. Yeh, “An AND-type match-line scheme for energy-efficient Content Addressable Memories,†in Solid State Circuits Conference, 2005. Digest of Technical Papers. ISSCC.2005 IEEE International, Feb. 2005, pp. 464–610 Vol. 1.

Y.-J. Chang and Y.-H. Liao, “Hybrid-type CAM design for both power and performance efficiency,†Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 16, no. 8, pp. 965–974, Aug. 2008.


Full Text: PDF [Full Text]

Refbacks

  • There are currently no refbacks.


Copyright © 2013, All rights reserved.| ijseat.com

Creative Commons License
International Journal of Science Engineering and Advance Technology is licensed under a Creative Commons Attribution 3.0 Unported License.Based on a work at IJSEat , Permissions beyond the scope of this license may be available at http://creativecommons.org/licenses/by/3.0/deed.en_GB.

Â